A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation
نویسندگان
چکیده
2-D Discrete Cosine Transform (DCT) applies on image data compression and saves more memories. In this paper, we use fast DCT algorithm, and propose a parallel-pipelined architecture to implement a 8 8× DCT/IDCT processor. This architecture involves two 8-point DCT processors, dual-bank of SRAM (128 words) and the coefficient ROM, three multiplexers, timing controller and 7-bit counter. The kernel arithmetic unit (AU) of 1-D DCT processor is designed by the CORDIC arithmetic. This architecture saves hardware and power consumption, and achieves high performance.
منابع مشابه
Design of 2d Discrete Cosine Transform Using Cordic Architectures in Vhdl
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